Modelling the Z80 instructions on the 6502
The Z80, 6502 register correspondence
| Z80 | 6502
|
|---|
| A, AF | A, SR
|
| B, C, BC | zc+1, zc, zc
|
| D, E, DE | ze+1, ze, ze
|
| H, L, HL | zl+1, zl, zl
|
| SP
|
| IX | zx
|
| IY | zy
|
zc, ze, zl, zx, zy are words in the zero page memory.
zs is a word for temporary values in the ZP.
XR is always 0 - this allows to have faster (HL)-based addressing
The 6502 and Z80 have several architectural differences which makes the emulation of several the Z80's features almost impossible:
- The stack pointer of the 6502 has its high byte always set to 1 but SP of the Z80 has 16 bits;
- The 6502 load instructions (LDA, TXA, LDY, PLA, ...) change SF and ZF, the Z80 load instructions don't change flags;
- The 6502 has the decimal mode and the Z80 has decimal correction instruction (DAA);
- The 6502 doesn't have parity, half-carry and subtraction flags;
- The 6502 uses the inverted carry flag for subtractions and comparisons;
- The 6502 instructions JSR and RET work with a stack a bit differently than the Z80 instructions CALL and RET;
- The 6502 has nothing similar to the Z80 instructions HALT, RETN and IM or to registers R and I;
- The Z80 instruction RETI is unique in the processor world;
- The 6502 doesn't have a special address space for input and output.
The 6502 instructions for the Z80 instructions
Links to similar tables
References